Design and Analysis for Low Power High Noise Tolerance Circuit
Ravi Prakash Sharma1, Anshul Jain1
Citation : Ravi Prakash Sharma,Anshul Jain, Design and Analysis for Low Power High Noise Tolerance Circuit International Journal of Innovative Research in Electronics and Communications 2015, 2(3) : 24-31
Digital integrated circuit noise has become one of the foremost issues in the design of very deep submicron VLSI chips. Noise in digital integrated circuits refers to any phenomenon that causes the voltage at a node to deviate from its nominal value. While these noises always existed, in the past they had little impact on the performance of integrated circuits and were often neglected. In this paper we have reduced the noise in deep submicron region. Thus we have to improve the noise tolerance of the dynamic circuits for better performance of the VLSI chips in deep submicron region at low supply voltages where the dynamic circuits are mostly affected by the noise. Thus a proposed a circuit which consume less power and have high noise tolerance.