We present ultra low power application, low power supply(vdd) of sub-threshold logic results in significant power reduction. The large supply voltage difference b/w sub-threshold core logic & i/o makes extremely challenging to convert signals from core circuit to i/o circuit in this we propose a level converter like static and dynamic level converters for sub-threshold logic high voltage clock signals needs to be delivered through separate clock path from core logic, leading clock synchronization problem b/w high voltage and low voltage clocks to overcome this issue we employed clock synchronizer.